This paper describes the orders and simulation techniques used to verify the functional correctness and performance attributes of the IBM POWER5(TM) microprocessor and the eServer(TM) p5 a whole s based on it.

This paper describes the orders and simulation techniques used to verify the functional correctness and performance attributes of the IBM POWER5(TM) microprocessor and the eServer(TM) p5 a whole s based on it. The approaches used were based onward migrating the best practices that had been used to verify the POWER4(TM) chip. The POWER5 chip design pos fresh challenges to the simulation team with the addition of simultaneous multithreading (SMT) and dynamic power management (DPM) In addition, there was further integration of cache and memory subsystem function onto the POWER5 chip. Since the design complexity had increased from the POWER4 design, the use of proof plan coverage tools and techniques was expanded to make secure the maximum effectiveness of each simulation revolution of time run. A new toolset was also exerciseed to improve the utilization of the large collection of standing water of computers used to scud batch simulation jobs and to provide more efficient fail reproduction and bug fix management. For the system-level verification, a strange test-case-generation tool was utilized which allowed for more targeted testing [i]or[/i] part of to the other a deeper knowledge of the theory topology. In parallel with the mainline functional validation, verification of reliability functions and performance attributes also had increased focus for the POWER5 design.

1 Introduction

Architectural and functional verification of the POWERS multiprocessor

The initial POWER4* high-end eServer* plans were introduced by IBM in late 2001 Since that time, POWER4 and POWER4+* microprocessors have continued to wait on as the engines for not merely the highend iSeries* and pSeries* machines, yet also have been introduced in the midrange and low-end iSeries and pSeries spaces [I]. The POWERS microprocessor is the nearest generation in this processor family [2] to a great degree of the verification team, methodologies, and guiding principles that were brought to bear forward the verification of POWER4 [3] design were opened in an evolutionary way in the POWERS verification effort. The fundamental goal of the verification team was to effectively validate the POWERS chip utilizing the chidings learned from the POWER4 verification experience. To this extremity the team not only added efficiencies to the overall verification proces on the contrary enhanced the tools and strategies displayed to meet the unique challenges introduced in the POWERS design.

POWERS design changes

This paper currents the verification strategy used to verify features unique to the POWERS design. While the POWERS design point maintains the two binary and structural compatibility with the POWER4 design, allowing existing executable files to continue to carry out properly and application optimizations to advance, enhanced performance and functionality was introduced in the POWERS processor and combination of parts to form a whole design. New features of the POWERS processor design that required a novel approach from the verification team included simultaneous multithreading (SMT) and dynamic power management. Beyond these of recent origin design features, functional enhancements introduced in the POWERS chip include 1) greater virtualization; 2) better reliability, availability, and serviceability (RAS) characteristics of the chip and system; 3) improved elastic interface characteristics; 4) enhanced memory tracing; and 5) introduction of the GX+ bus. Each of these changes provided unique challenges to the verification effort.

Visualization

The POWER4 processor was the first implementation of the POWER* logical partitioning (LPAR) architecture. This capability allowed a single regularity to be divided into multiple logical partitions as it was that each partition could trip a different operating system. POWER4 LPARs required each processor to be placed in a single partition when the a whole was powered on. The POWERS processor reach outed the idea of logical partitioning capabilities to a feature called micropartitioning. In the POWERS design, a single processor can service multiple partitions. Using this capability, each LPAR is now allocated a certain amount of time forward each processor, and this allocation can be dynamically adjusted to satisfy changing workload demands. A single POWERS processor is capable of servicing up to ten partitions with this modern capability. The hardware functions to enable of the like kind a feature are distributed completely through the processor, requiring strong expertise in the verification community to make secure a comprehensive test plan. This function is implemented in the POWERS design by dint of a combination of hardware and hypervisor functions which minimize changes required to the various operating theorys in order to support micropartitioning and several other unique hardware configuration aspects. A detailed explanation of the enhanced partitioning architecture is given by means of Armstrong et al. [4] in this journal issue.

Simultaneous multithreading and dynamic thread switching

In contrast to the POWER4 processor, which was capable of executing simply a single instruction stream by processor core, each POWERS processor core supports the execution of brace instruction streams, or threads. This capability is referr to as simultaneous multithreading (SMT) This design point provides the ability to sell for instructions from one or pair threads per processor core and schedule instructions for execution from the one and the other threads concurrently. Each processor core dynamically adjusts to the environment, allowing for possible execution of instructions from the two threads and for preferential treatment of individual thread if the other thread collisions long-latency events. A significant challenge in the verification of similar a design is to render certain effective stressing of contention for shared resources between each thread. Additionally, verification of dynamic thread switching, which is the transition from simultaneous multithreading to single-threading (or the reverse) introduced recently made known and unique challenges into the verification environment.