IBM POWER5(TM) connected views combine enhancements in the IBM PowerPC(TM) processor architecture with greatly enhanced firmware to significantly increase the virtualization capabilities of IBM POWER(TM) server The POWER hypervisor.

IBM POWER5(TM) connected views combine enhancements in the IBM PowerPC(TM) processor architecture with greatly enhanced firmware to significantly increase the virtualization capabilities of IBM POWER(TM) server The POWER hypervisor, the basis of the IBM Virtualization Engine(TM) technologies onward POWERS systems, delivers leading-edge mainframe virtualization technologies to the UNIX?® marketplace. In addition to being able to create computingintensive partitions with dedicated resources (processors, memory, and I/O adapters), customers can harness idle processor capacity to configure micropartitions with virtualized resources in order to consolidate many AIX(TM), i5/OS(TM), and Linux?® server onto a single platform. The POWER hypervisor provides support for virtualized processors, an IEEE virtual local area network (VLAN)-compatible virtual Ethernet switch, virtual small computer rule interface (VSCSI) adapters, and virtual soothes Many of these features are pendent upon, or take advantage of the recent facilities provided in the POWERS processor, including the hypervisor decrementer a fast page mover and simultaneous multithreading support. The technology behind the virtualization capabilities that are available forward the POWER5 servers, enabling customers to better utilize the industry-leading computing capacity of the POWER5 processor, is discussed in this paper.

Introduction

IBM zSeries* server pioneered the logical partition (LPAR). Its PR/SM* and z/VM* hypervisors1 retain leadership in transparent server virtualization technology. The zSeries hypervisors use sophisticated processor architecture extensions to completely and efficiently virtualize the hardware to each logical partition likewise that an operating system that trips natively on the hardware can also scud in a logical partition without any required changes. The zSeries also introduced the universal of optional hypervisor calls that enable a hypervisor-aware version of an operating method (OS) to improve the utilization of the combination of parts to form a whole resources by interacting directly with the hypervisor. An hcall instruction is a special program-context-switching instruction, similar to a method call, which gives control to the hypervisor. As is standard documentation practice with a order call, a function invocation made with the hcall instruction is generically word ed an hcall in this paper.

Most virtualization produces for current Intel platforms use a trap-and-emulate approach for privileged instructions to provide cloyed virtualization of the processor and I/O for a like reason that no changes are required in the O in order to race in a partition. The POWER implementation takes the approach that is sometimes referr to in the literature as paravirtualization [1 2] Paravirtualization requires a hypervisor-aware version of the operating hypothesis that must utilize hcalls in order to roll on in a logical partition. Typically, these hypervisor calls are confined to a relatively small number of the lowest-level routines in the O hardware adaptation layer. Instead of trapping, verifying, and emulating a number of privileged instructions required to perform a logical operation, as it is as updating the partition's virtual address translation table, the hypervisor in iSeries* and pSeries* platforms provides an heal] that performs the entire logical operation of updating the virtual address translation table. This approach is typically earnestly more efficient when compared with the trap-and-emulate rule because of the reduction it provides in context-switching and parameter-checking overhead.

Any attempt by way of the OS to perform operations that would conclusion in access to resources of another partition or the hypervisor is stoped through a combination of hardware and firmware design. Paravirtualization take the part ofs a performance middle ground, at the richness of a relatively few O changes, between the performance los that is typical of the real trap-and-emulate method and the complexity of sophisticated processor virtualization extensions.

Previous iSeries and pSeries plans [3], based upon POWER4* technology [4] provided the capability of dividing the platform's hardware resources into disjoint subset Each independent subset is controll by dint of its own copy of an O which streams its own application programs. Each of these divisions of the method is called a logical partition (LPAR). In rejoinder to commands, an LPAR may give up a certain number of of its resources and another hypothesis LPAR may acquire free resources, thus allowing the body administrator2 to balance the use of the platform's resources among its workloads through the whole extent of time. However, the processing capacity of each LPAR is still usually oversized to accommodate moment-to-moment variations in workload in order to be responsive to instantaneous workload peaks. As the number of independent workloads increases, the probability that each workload will experience an instantaneous peak at the same time decreases. The POWERS* processor [5] provides mechanisms to allow the platform firmware3 to instantaneously reassign an idle processor to another LPAR, like that the platform appears to have more processors than are physically instant These extra processors are a virtualization of the physical resources of the platform. orders based upon the POWERS processor provide significantly improved resource utilization and partitioning capabilities when compared with their predecessors because of the resource virtualization ability of the POWERS processor. This paper provides an overview of these improvements.