The heart and chief part of all computer systems remains the microprocessor.

The heart and chief part of all computer systems remains the microprocessor. In this issue we describe sum of two units new microprocessors, the POWER5(TM) and small room microprocessors. Each is innovative in its approach and is part of a total order design. Each leverages technology and uses the available increased transistor density to incorporate more a whole function onto a single die than prior connected views have done.

The POWER5 chip continues along the path first introduced with POWER4(TM) rules in 2001-a dualcore, high-performance total theory design. It extends performance significantly beyond that achieved with POWER4 arrangements Each POWERS core is capable of simultaneously executing sum of two units independent threads of instructions. With couple cores available, each POWER5 chip can appear to software as four independent processors. With up to 64 processors forward 32 chips, POWER5 systems have achieved record performance flats on a wide range of industry-standard benchmarks. In addition to the raw performance available, recent visualization capabilities allow up to ten regularitys to share a single physical processor and provide up to 254 virtual schemes on a single 64-way eServer(TM) pSeries(TM) p5-595 rule This capability makes possible more effective and greater utilization of plan resources. The visualization technologies introduced with POWERS bodys include the ability for multiple virtual regularitys to physically share disks and Ethernet connections, enabling easier connected view management and improving the total splendor of ownership.

The Cell plot was driven by the ne to satisfy requirements for the next-generation entertainment plans The Cell processor exploits the increased transistor density according to incorporating two types of processors onward the die-a dual-threaded 64-bit Power Architecture(TM) compliant power processor component part (PPE) and eight newly architected synergistic processor ultimate parts (SPEs). The PPE and the SPE include single instruction, multiple data (SIMD) capabilities.

Both the POWER5 and small cavity projects included resources from across a wide range of IBM disclosure facilities around the world. They are in deed achievements of Team IBM. This design philosophy includes all aspects of a arrangement from raw technology to chip architecture and design to software considerations. The small room project further benefited from participation by dint of engineers from Sony Computer Entertainment Incorporated (SCEI) and the Toshiba Corporation.

The first paper in this issue, at Sinharoy et al., describes the POWER5 microarchitecture and the microarchitecture of combination of parts to form a wholes based on the POWER5 chip. As a successor to the POWER4 design, the paper describes the changes made for the POWER5 method structure.

Enhanced virtualization functions implemented by dint of a combination of POWER5 hardware and firmware allow customers to realize the well stocked [i]or[/i] provided benefit of POWER5 systems and to more effectively utilize all available connected view resources. These capabilities are described in the paper by dint of Armstrong et al.

All combination of parts to form a wholes require operating system support to exploit their capabilities. Linux(TM) and AIX?® support for POWER5 bodys is described in the paper from Mackerras et al. The POWER5 hardware has the ability to operate in either single-threaded or simultaneously multithreaded customs of operation. Operating system decisions upon when to switch from undivided mode to the other and by what means processes are scheduled across available connected view resources are described in this paper.

POWER5 schemes include many new features. Simultaneous multithreading and the ability to manage power consumption by means of dynamically turning clocks on and on the farther side to parts of the POWER5 chip are examples of capabilities that significantly tax the verification proces The paper by the agency of Victor et al. describes the approach used and near of the new tools engrossed in verifying the POWER5 system

Simultaneous multithreading allows single to more fully utilize theory resources to achieve higher of the same heights of performance. In cases where either execution units are choke to full utilization or available bandwidth between a POWER5 chip and other constituents of the system is completely utilized, simultaneous multithreading will not provide a benefit. the couple POWER4 and POWER5 systems include true powerful hardware performance monitors and toolsets. These capabilities allow single to gain insight into regularity performance. The paper by Mathis et al. explores this capability across a range of workloads that exhibit high, medium, subdued and even negative performance benefits from enabling simultaneous multithreading.

Verifying a scheme can be only as religious as the test cases allow. Classical simulation techniques rely in succession the verification engineer to design proofs to validate the proper functioning of specific features included in a design. With the increasing number and complexity of functions being incorporated onto our chips, realizing 100% coverage becomes more problematic with each fresh chip generation. Functional formal verification, the proces of proving that a design adheres to its specifications, addresses this position However, full formal verification of all aspects of a design with this technology is not to this time feasible with chips the size and complexity of the POWERS chip. Despite this, functional formal verification has played an important character in the IBM design verification proces dating back to the POWER3(TM) chip, which was generally available in 1998 The paper by the agency of Gott et al. describes its use in the verification of the POWERS processor and the communication subsystem